Optimizing Control Factors for Threshold Voltage and Leakage Current in 32 nm PMOS Transistors with the Taguchi Method
Keywords:
Index Terms, 32 nm PMOS TiO2/WSix, high-k/metal gate, threshold voltage, leakage current, Taguchi methodAbstract
This study utilizes the Taguchi method to optimize control factors for achieving optimal response characteristics, specifically focusing on the threshold voltage (Vth) and leakage current (Ileak) of a PMOS transistor with a gate length of 32 nm. The PMOS transistor design incorporates a high permittivity material (high-k) as the dielectric layer and metal gate materials such as Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX). The optimization of control factors in PMOS device design is conducted using the Taguchi Orthogonal Array Method, with Signal-to-Noise Ratio (SNR) analysis employing Nominal-the-Best (NTB) SNR for Vth and Smaller-the-Better (STB) SNR for Ileak. Four manufacturing control factors and two noise factors are considered to optimize response characteristics and identify the optimal design parameter combination. The analysis reveals that the Halo implantation tilting angle exerts the most significant influence, with a 55.52% effect on the SNR of Ileak. The study demonstrates that Vth values exhibit minimal variance, with a mean value approximately 0.289 V ± 12.7%, while Ileak remains below 100 nA/µm, aligning with projections outlined in the International Technology Roadmap for Semiconductors (ITRS)
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References
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